1. Field of the Invention
The present invention relates to a memory circuit and a method for writing into a target memory area, particularly to memory circuits with non-volatile memory elements, for example integrated circuits (IC) for chip cards.
2. Description of the Related Art
Nowadays, non-volatile memories (NVM) such as flash memories, are used in many products, for example in the field of embedded or integrated systems, respectively, and here particularly in the field of chip card ICs. During programming or writing of data, respectively, the problem of a shift of threshold voltages of the field-effect transistors used in those memories (flash FET of flash memory) arises in many types of non-volatile memories, particularly area-optimized types of non-volatile memories, and here particularly flash memories. The resulting problem is that frequently not only the threshold voltages of the selected memory cells to be programmed are altered, but also the threshold voltages of memory cells lying in the same sector, which should actually remain unaltered, are altered slightly. This effect or mechanism, respectively, is also referred to as “drain disturb”, and can cause data loss of the disturbed memory cells by accumulation of the threshold voltage changes after many programmings within the respective sector. The too heavy accumulation of disturbances is avoided by recopying and refreshing the respective data on time. This mechanism is referred to as disturb handling and can be performed in different ways.
Disturb handling consists of explicitly storing a count with every programming process. If the difference of different counts in one sector becomes too large, which means exceeds a predetermined value, the areas with the smallest counts are recopied, which means the same are subject to a refresh. A disadvantage of this method is particularly the required implementation of the count in every separately programmable area (page), which is typically 16 bit or 32 bit per separately programmable area, and has thus typically a requirement of several percent of a memory field, typically approximately 3% of a memory field. Additionally, a further advantage is the required search of all counts within a sector when data are to be changed in this sector. Thus, on the one hand, this embodiment of disturb handling requires a high amount of memory for storing the counts and, on the other hand, a long runtime for searching and evaluating the counts.
A second method of disturb handling is an arbitrary selection of a programmable area for refresh. In this method, in every programming of a memory area of a sector, an arbitrary decision is made with a certain probability, whether an also arbitrarily selected area within the same sector will be recopied, which means subjected to a refresh. By determining or selecting the probability for reprogramming, it is ensured that statistically all areas are reprogrammed in time, before data loss occurs. A particular disadvantage of this method is the fact that due to the statistical nature of the method, either the reprogramming probability and thus the reprogramming rate has to be selected so high to ensure timely refresh of the data in any case, or, on the other hand, a certain probability for data loss has to be taken into account due to recopying of an area not being performed in time. Due to the length of a write process typical for a flash memory, compared to a read process, the effective write speed, which a later user realizes, is heavily reduced at a reprogramming probability, which leads to a high reprogramming rate. Additionally, with a recopying rate selected too high, the life time of a memory circuit is significantly decreased, since the average life time of a corresponding memory system is typically significantly determined by the number of write processes, so that with every write process but also with every recopy process, the remaining residual life time is decreased. If, however, the reprogramming probability is chosen such that a lower reprogramming rate results, an increased probability of data loss exists, which cannot be tolerated.
The second mentioned method is also described in U.S. Pat. No. 5,625,791. In this patent, a chip card with non-volatile electrically erasable and programmable memory is described, in which a method for automatical refresh of the content of certain zones of the memory is implemented, to avoid the risk due to aging of an EEPROM memory (EEPROM=electrically erasable programmable read only memory). The refresh described there can be performed after predetermined time intervals or at the end of predetermined number of usages, or also as a routine, whenever the card is supplied with current. If only part of a zone is addressed in the step of refreshing, the address of this part of the zone is determined by a random generator. In other words, the above-mentioned US patent describes the usage of a random number generator for determining any refresh address, when the chip card is powered up.
The U.S. Pat. No. 6,160,738 describes a non-volatile semiconductor memory system with a grid of non-volatile memory cells, which is divided into erasure blocks and refresh blocks. Additionally, the memory system has an arrangement of intermediate marking cells, wherein each intermediate marking cell is associated with a refresh block and buffers information about the refresh state of the associated refresh block. In other words, the recited US patent describes the usage of a separate arrangement of intermediate marking memories (flag array), where the refresh state of an associated block is stored and erased again separately.
The US patent application US 2004/0170060 A1 describes a semiconductor memory device with a detection means, which divides the semiconductor memory into refresh zones and determines a refresh zone which comprises a write target during a write process. The detection means refreshes the sectors belonging to the associated refresh zone, which had been determined by detection means, one after the other.